This invention is in the field of solid-state memories. Embodiments of this invention are directed to metal-oxide-semiconductor (MOS) one-time-programmable (OTP) memory cells and methods of constructing the same.
Electrically-programmable memory has been a staple form of solid-state memory for a number of years. Various forms of electrically-programmable memory are well-known in the art, including electrically-programmable read-only memory (EPROM) that is erasable by ultraviolet light, electrically-erasable programmable read-only memory (EEPROM), which is also referred to as electrically-alterable programmable read-only memory (EAPROM), “flash” EEPROM in which blocks of memory cells can be erased in a single erase operation, and the like. In general, electrically-programmable solid-state memory is attractive because of its non-volatility, in that the stored contents remain stored after power has been removed from the memory device. As such, electrically-programmable solid-state memory is often used to store program instructions, configuration data, and other information that is required or useful to an integrated circuit upon power-up. Flash EEPROM is now also often used as non-volatile data storage, for example in portable audio players, smartphones, tablet computers, and the like.
One class of electrically-programmable solid-state memory that is now commonplace is referred to as “one-time programmable”, or “OTP”, memory. By virtue of its construction, OTP memory cells cannot be erased once programmed, and hence are “one-time programmable”. A conventional OTP memory cell typically consists of a metal-oxide-semiconductor (MOS) transistor, with a floating gate electrode (i.e., a gate electrode that is not electrically connected to any other node in the integrated circuit). In manufacture, the unprogrammed state of the OTP cell, in which no charge is trapped on the floating gate electrode, is enforced by ultraviolet exposure or the like. Programming of an OTP cell is performed by driving or pulsing a relatively large drain-to-source voltage at the transistor, resulting in channel hot carrier (CHC) conduction to the floating gate. The carriers (holes or electrons, as the case may be) that become trapped at the floating gate apply a gate bias to the transistor. Typically, this mechanism has a self-limiting effect during programming. After programming, sensing of the data state of the memory cell is performed by applying a drain-to-source voltage at a “read” level (lower than the programming voltage); the resulting source-drain current is relatively high (current Ion) for programmed cells, and relatively low (current Ioff) for cells that were not programmed. The ratio of Ion/Ioff is typically several orders of magnitude, with Ion typically on the order of microamperes and Ioff typically on the order of picoamperes. A high Ion/Ioff ratio is facilitates data read speed, and increases noise margin. Typically, OTP cell transistors are constructed with a channel length on the order of the minimum for the integrated circuit, for chip area efficiency.
Techniques for increasing the Ion/Ioff ratio of OTP memory cells are known in the art. One technique is simply to increase the channel width of the memory cell transistor to increase its programmed state current Ion, but this necessarily increases the chip area required to realize the OTP array, especially if the number of memory cells in the array is significant. Other conventional approaches for increasing the programmed state current (i.e., Ion) of the OTP memory cell require undesirable increases in programming voltage and programming time, as described in U.S. Pat. No. 7,244,651, commonly assigned herewith and incorporated hereinto by this reference. By way of further background, this U.S. Pat. No. 7,244,651 itself describes another technique for increasing the Ion/Ioff ratio, specifically by decreasing the leakage (i.e., Ioff) current.
By way of further background, the ion implantation of fluorine into the active regions of MOS transistors is known. Lin et al., “The Effect of Fluorine on MOSFET Channel Length”, Elec. Device Letters, Vol. 14, No. 10 (IEEE, October 1993), pp. 469-71, incorporated herein by reference, describes the implantation of fluorine into the source and drain regions of MOS transistors (i.e., specifically into the “lightly-doped drain” implanted regions) after formation of the polysilicon gate electrode; this paper reports that the fluorine results in a smaller channel length reduction, by retarding phosphorous lateral diffusion. Goto et al., “A Triple Gate Oxide CMOS Technology Using Fluorine Implant for System-on-a-Chip”, Digest of Technical Papers: 2000 Symposium on VLSI Technology, Paper 15.3 (IEEE, 2000), pp. 148-49, describes the implantation of fluorine into the low power CMOS active region, prior to formation of the gate oxide and gate electrode, to reduce gate leakage current.